From 16842d08694f82f0c65957340ea801e0b7da0a42 Mon Sep 17 00:00:00 2001 From: Michael Reeves Date: Fri, 30 Jan 2026 20:57:45 +1100 Subject: [PATCH 1/9] arm64: dts: apple Correct M3 MacBook Air board numbers The board numbers listed in t8122-jxxx.dtsi (J513, J515) were used internally for M3 MacBook Air prototypes and appear in leaks [0], however, no released product seems to exist with them, with the M3 MacBook Air line instead using J613 and J615 [1][2]. Thus, correct these numbers. [0] https://9to5mac.com/2023/04/10/15-inch-macbook-air-panel -production-reportedly-ramping-up-ahead-of-upcoming-launch/ [1] https://en.wikipedia.org/wiki/List_of_Apple_codenames [2] My own personal testing on my 13-inch M3 MacBook Air Signed-off-by: Michael Reeves --- arch/arm64/boot/dts/apple/t8122-jxxx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi index fedf09bf22c194..32fd34af75e991 100644 --- a/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8122-jxxx.dtsi @@ -4,7 +4,7 @@ * * This file contains parts common to all Apple M3 devices using the t8122. * - * target-type: J433, J434, J504, J513, J515 + * target-type: J433, J434, J504, J613, J615 * * Copyright The Asahi Linux Contributors */ From ff49d909b31ed21360d933bb88238b92a7a98353 Mon Sep 17 00:00:00 2001 From: Michael Reeves Date: Fri, 30 Jan 2026 21:11:21 +1100 Subject: [PATCH 2/9] arm64: dts: apple: Add cpufreq and OPP to M3 (t8122) In the Apple M3 (t8122) device tree: - Add the following properties to each CPU node - operating-points-v2 - capacity-dmips-mhz - performance-domains - Add operating point tables for p-cores and e-cores - Add cpufreq hardware controller nodes (for both p-cluster and e-cluster) Signed-off-by: Michael Reeves --- arch/arm64/boot/dts/apple/t8122.dtsi | 195 +++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8122.dtsi b/arch/arm64/boot/dts/apple/t8122.dtsi index 2e2cf30f3cd510..0e75626c1b2773 100644 --- a/arch/arm64/boot/dts/apple/t8122.dtsi +++ b/arch/arm64/boot/dts/apple/t8122.dtsi @@ -62,6 +62,9 @@ reg = <0x0 0x0>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; next-level-cache = <&l2_cache_0>; i-cache-size = <0x20000>; d-cache-size = <0x10000>; @@ -73,6 +76,9 @@ reg = <0x0 0x1>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; next-level-cache = <&l2_cache_0>; i-cache-size = <0x20000>; d-cache-size = <0x10000>; @@ -84,6 +90,9 @@ reg = <0x0 0x2>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; next-level-cache = <&l2_cache_0>; i-cache-size = <0x20000>; d-cache-size = <0x10000>; @@ -95,6 +104,9 @@ reg = <0x0 0x3>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; next-level-cache = <&l2_cache_0>; i-cache-size = <0x20000>; d-cache-size = <0x10000>; @@ -106,6 +118,9 @@ reg = <0x0 0x10100>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; next-level-cache = <&l2_cache_1>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; @@ -117,6 +132,9 @@ reg = <0x0 0x10101>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; next-level-cache = <&l2_cache_1>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; @@ -128,6 +146,9 @@ reg = <0x0 0x10102>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; next-level-cache = <&l2_cache_1>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; @@ -139,6 +160,9 @@ reg = <0x0 0x10103>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; next-level-cache = <&l2_cache_1>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; @@ -159,6 +183,165 @@ }; }; + ecluster_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <1>; + clock-latency-ns = <7500>; + opp-microwatt = <26000>; + }; + opp02 { + opp-hz = /bits/ 64 <912000000>; + opp-level = <2>; + clock-latency-ns = <20000>; + opp-microwatt = <56000>; + }; + opp03 { + opp-hz = /bits/ 64 <1284000000>; + opp-level = <3>; + clock-latency-ns = <22000>; + opp-microwatt = <88000>; + }; + opp04 { + opp-hz = /bits/ 64 <1752000000>; + opp-level = <4>; + clock-latency-ns = <30000>; + opp-microwatt = <155000>; + }; + opp05 { + opp-hz = /bits/ 64 <2004000000>; + opp-level = <5>; + clock-latency-ns = <35000>; + opp-microwatt = <231000>; + }; + opp06 { + opp-hz = /bits/ 64 <2256000000>; + opp-level = <6>; + clock-latency-ns = <39000>; + opp-microwatt = <254000>; + }; + opp07 { + opp-hz = /bits/ 64 <2424000000>; + opp-level = <7>; + clock-latency-ns = <53000>; + opp-microwatt = <351000>; + }; + }; + + pcluster_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp01 { + opp-hz = /bits/ 64 <660000000>; + opp-level = <1>; + clock-latency-ns = <9000>; + opp-microwatt = <133000>; + }; + opp02 { + opp-hz = /bits/ 64 <924000000>; + opp-level = <2>; + clock-latency-ns = <19000>; + opp-microwatt = <212000>; + }; + opp03 { + opp-hz = /bits/ 64 <1188000000>; + opp-level = <3>; + clock-latency-ns = <22000>; + opp-microwatt = <261000>; + }; + opp04 { + opp-hz = /bits/ 64 <1452000000>; + opp-level = <4>; + clock-latency-ns = <24000>; + opp-microwatt = <345000>; + }; + opp05 { + opp-hz = /bits/ 64 <1704000000>; + opp-level = <5>; + clock-latency-ns = <26000>; + opp-microwatt = <441000>; + }; + opp06 { + opp-hz = /bits/ 64 <1968000000>; + opp-level = <6>; + clock-latency-ns = <28000>; + opp-microwatt = <619000>; + }; + opp07 { + opp-hz = /bits/ 64 <2208000000>; + opp-level = <7>; + clock-latency-ns = <30000>; + opp-microwatt = <740000>; + }; + opp08 { + opp-hz = /bits/ 64 <2400000000>; + opp-level = <8>; + clock-latency-ns = <33000>; + opp-microwatt = <855000>; + }; + opp09 { + opp-hz = /bits/ 64 <2568000000>; + opp-level = <9>; + clock-latency-ns = <34000>; + opp-microwatt = <1006000>; + }; + opp10 { + opp-hz = /bits/ 64 <2724000000>; + opp-level = <10>; + clock-latency-ns = <36000>; + opp-microwatt = <1217000>; + }; + opp11 { + opp-hz = /bits/ 64 <2868000000>; + opp-level = <11>; + clock-latency-ns = <41000>; + opp-microwatt = <1534000>; + }; + opp12 { + opp-hz = /bits/ 64 <2988000000>; + opp-level = <12>; + clock-latency-ns = <42000>; + opp-microwatt = <1714000>; + }; + opp13 { + opp-hz = /bits/ 64 <3096000000>; + opp-level = <13>; + clock-latency-ns = <44000>; + opp-microwatt = <1877000>; + }; + opp14 { + opp-hz = /bits/ 64 <3204000000>; + opp-level = <14>; + clock-latency-ns = <46000>; + opp-microwatt = <2159000>; + }; + opp15 { + opp-hz = /bits/ 64 <3324000000>; + opp-level = <15>; + clock-latency-ns = <62000>; + opp-microwatt = <2393000>; + turbo-mode; + }; + opp16 { + opp-hz = /bits/ 64 <3408000000>; + opp-level = <16>; + clock-latency-ns = <62000>; + opp-microwatt = <2497000>; + turbo-mode; + }; + opp17 { + opp-hz = /bits/ 64 <3504000000>; + opp-level = <17>; + clock-latency-ns = <62000>; + opp-microwatt = <2648000>; + turbo-mode; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&aic>; @@ -193,6 +376,18 @@ /* Required to get >32-bit DMA via DARTs */ dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; + cpufreq_e: cpufreq@210e20000 { + compatible = "apple,t8122-cluster-cpufreq", "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x10e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + cpufreq_p: cpufreq@211e20000 { + compatible = "apple,t8122-cluster-cpufreq", "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x11e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + i2c0: i2c@235010000 { compatible = "apple,t8122-i2c", "apple,t8103-i2c"; reg = <0x2 0x35010000 0x0 0x4000>; From ddb3a578ffde81b26826e1e5d4a9f0e57c9d2fe2 Mon Sep 17 00:00:00 2001 From: Michael Reeves Date: Fri, 30 Jan 2026 21:27:05 +1100 Subject: [PATCH 3/9] arm64: dts: apple: Add SMC to M3 (t8122) device tree Adds the System Management Contorller (SMC) to the Apple M3 SoC (t8122) device tree, including the SMC mailbox and the SMC itself, with GPIO and hwmon children. Signed-off-by: Michael Reeves --- arch/arm64/boot/dts/apple/t8122.dtsi | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8122.dtsi b/arch/arm64/boot/dts/apple/t8122.dtsi index 0e75626c1b2773..926bb9076af83c 100644 --- a/arch/arm64/boot/dts/apple/t8122.dtsi +++ b/arch/arm64/boot/dts/apple/t8122.dtsi @@ -599,6 +599,37 @@ interrupts = ; }; + smc_mbox: mbox@2ec408000 { + compatible = "apple,t8122-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0xec408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + + smc: smc@2ec400000 { + compatible = "apple,t8122-smc", "apple,smc"; + reg = <0x2 0xec400000 0x0 0x4000>, + <0x2 0xede00000 0x0 0x100000>; + reg-names = "smc", "sram"; + mboxes = <&smc_mbox>; + + smc_gpio: gpio { + compatible = "apple,smc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + smc_hwmon: hwmon { + compatible = "apple,smc-hwmon"; + }; + }; + pinctrl_smc: pinctrl@2ec820000 { compatible = "apple,t8122-pinctrl", "apple,t8103-pinctrl"; reg = <0x2 0xec820000 0x0 0x4000>; From 6445ee72419d3489d1a474a233aafbef79b1b328 Mon Sep 17 00:00:00 2001 From: Michael Reeves Date: Fri, 30 Jan 2026 21:43:14 +1100 Subject: [PATCH 4/9] arm64: dts: apple: Add MTP DockChannel to M3 device tree The internal keyboard and trackpad HID on MacBook variants of the Apple M3 (t8122) SoC are connected through a Apple -developed protocol called DockChannel and mediated by a coprocessor known as the Multi-Touch Processor (MTP). This commit adds the nessecary device tree nodes to the M3's device tree for internal HID to work. It is disabled by default, to be enabled only in MacBook board files where it is tested and confirmed to work. Co-developed-by: Alyssa Milburn Signed-off-by: Alyssa Milburn Signed-off-by: Michael Reeves --- arch/arm64/boot/dts/apple/t8122.dtsi | 79 ++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8122.dtsi b/arch/arm64/boot/dts/apple/t8122.dtsi index 926bb9076af83c..ec740019963c4f 100644 --- a/arch/arm64/boot/dts/apple/t8122.dtsi +++ b/arch/arm64/boot/dts/apple/t8122.dtsi @@ -671,6 +671,85 @@ , ; }; + + mtp: mtp@2fa400000 { + compatible = "apple,t8122-mtp", "apple,t8122-rtk-helper-asc4", "apple,mtp", "apple,rtk-helper-asc4"; + reg = <0x2 0xfa400000 0x0 0x4000>, + <0x2 0xfac00000 0x0 0x100000>; + reg-names = "asc", "sram"; + + mboxes = <&mtp_mbox>; + iommus = <&mtp_dart 1>; + #helper-cells = <0>; + + status = "disabled"; + }; + + mtp_mbox: mbox@2fa408000 { + compatible = "apple,t8122-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0xfa408000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + + #mbox-cells = <0>; + + status = "disabled"; + }; + + mtp_dart: iommu@2fa808000 { + compatible = "apple,t8122-dart", "apple,t8110-dart"; + reg = <0x2 0xfa808000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = ; + + #iommu-cells = <1>; + + status = "disabled"; + }; + + mtp_dockchannel: fifo@2fab30000 { + compatible = "apple,t8122-dockchannel", "apple,dockchannel"; + reg = <0x2 0xfab14000 0x0 0x4000>; + reg-names = "irq"; + interrupt-parent = <&aic>; + interrupts = ; + + ranges = <0 0x2 0xfab30000 0x20000>; + nonposted-mmio; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-controller; + #interrupt-cells = <2>; + + status = "disabled"; + + mtp_hid: input@8000 { + compatible = "apple,dockchannel-hid"; + reg = <0x8000 0x4000>, + <0xc000 0x4000>, + <0x0000 0x4000>, + <0x4000 0x4000>; + reg-names = "rmt-config", "rmt-data", "config", "data"; + + iommus = <&mtp_dart 1>; + + interrupt-parent = <&mtp_dockchannel>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + apple,fifo-size = <0x800>; + apple,helper-cpu = <&mtp>; + }; + }; }; }; From 0156b7c52fd54892796b6a8166f329f7dc72ecc9 Mon Sep 17 00:00:00 2001 From: Michael Reeves Date: Fri, 30 Jan 2026 21:52:08 +1100 Subject: [PATCH 5/9] arm64: dts: apple: Add NVMe nodes to M3 (t8122) device tree On Apple Silicon, NVMe communication is mediated by a coprocessor known as the ANS, and protected by its own IOMMU known as the SART. Add the following nodes to the M3 (t8122) device tree: - Mailbox for the ANS coprocessor - SART (IOMMU for the ANS coprocessor) - The NVMe / ANS coprocessor itself Signed-off-by: Michael Reeves --- arch/arm64/boot/dts/apple/t8122.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8122.dtsi b/arch/arm64/boot/dts/apple/t8122.dtsi index ec740019963c4f..9e0761943660d5 100644 --- a/arch/arm64/boot/dts/apple/t8122.dtsi +++ b/arch/arm64/boot/dts/apple/t8122.dtsi @@ -750,6 +750,46 @@ apple,helper-cpu = <&mtp>; }; }; + + ans_mbox: mbox@309408000 { + compatible = "apple,t8122-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x3 0x09408000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + + #mbox-cells = <0>; + + power-domains = <&ps_ans>; + }; + + sart: sart@30dc50000 { + compatible = "apple,t8122-sart", "apple,t6000-sart"; + reg = <0x3 0x0dc50000 0x0 0x10000>; + power-domains = <&ps_ans>; + }; + + nvme: nvme@30dcc0000 { + compatible = "apple,t8122-nvme-ans2", "apple,nvme-ans2"; + reg = <0x3 0x0dcc0000 0x0 0x60000>, + <0x3 0x09400000 0x0 0x4000>; + reg-names = "nvme", "ans"; + + interrupt-parent = <&aic>; + interrupts = ; + + mboxes = <&ans_mbox>; + apple,sart = <&sart>; + + power-domains = <&ps_ans>, <&ps_apcie_phy_sw>; + power-domain-names = "ans", "apcie_phy_sw"; + resets = <&ps_ans>; + }; }; }; From 1b5d498ef8fd4b735265eb3851e27b2da4d458c5 Mon Sep 17 00:00:00 2001 From: Michael Reeves Date: Fri, 30 Jan 2026 22:06:07 +1100 Subject: [PATCH 6/9] arm64: dts: apple: Add J613 board variant of M3 (t8122) Add a device tree for the Apple MacBook Air (13-inch, M3, 2024) board variant of the M3 (t8122), known as J613. It enables and configures the keyboard backlight and internal HID nodes, as it is a laptop variant which has these devices. Also add this new device tree to the Makefile, so it is built. Signed-off-by: Michael Reeves --- arch/arm64/boot/dts/apple/Makefile | 1 + arch/arm64/boot/dts/apple/t8122-j613.dts | 79 ++++++++++++++++++++++++ 2 files changed, 80 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8122-j613.dts diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index a17f75bd5a2750..f01cc6f5e9160f 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -92,3 +92,4 @@ dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j493.dtb dtb-$(CONFIG_ARCH_APPLE) += t8122-j504.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8122-j613.dtb diff --git a/arch/arm64/boot/dts/apple/t8122-j613.dts b/arch/arm64/boot/dts/apple/t8122-j613.dts new file mode 100644 index 00000000000000..61ec12759c638b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8122-j613.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Air (13-inch, M3, 2024) + * + * target-type: J613 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8122.dtsi" +#include "t8122-jxxx.dtsi" +#include + +/ { + compatible = "apple,j613", "apple,t8122", "apple,arm-platform"; + model = "Apple MacBook Air (13-inch, M3, 2024)"; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm1 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; +}; + +&framebuffer0 { + // panel = &panel; + power-domains = <&ps_disp_cpu>, <&ps_dptx_ext_phy>; +}; + +&fpwm1 { + status = "okay"; +}; + +&mtp { + status = "okay"; +}; + +&mtp_mbox { + status = "okay"; +}; + +&mtp_dart { + status = "okay"; +}; + +&mtp_dockchannel { + status = "okay"; +}; + +&mtp_hid { + apple,afe-reset-gpios = <&smc_gpio 8 GPIO_ACTIVE_LOW>; + apple,stm-reset-gpios = <&smc_gpio 24 GPIO_ACTIVE_LOW>; + + multi-touch { + firmware-name = "apple/tpmtfw-j613.bin"; + }; + + keyboard: keyboard { + hid-country-code = <0>; + apple,keyboard-layout-id = <0>; + }; + + stm { + }; + + actuator { + }; + + tp_accel { + }; +}; From 9392ee90c4861242e4c38d10c3c9234fa0db044c Mon Sep 17 00:00:00 2001 From: Alyssa Milburn Date: Sat, 31 Jan 2026 12:27:37 +1100 Subject: [PATCH 7/9] arm64: dts: apple: Add PCIe nodes for t8122 This only includes the first port, because it's the only port that is present on my hardware, and only includes the pwren gpio for J613. Uses the t6020 base compatible as that is what the M3 hardware appears to be compatible with, rather than the configuration applied by the generic base compatible. Signed-off-by: Alyssa Milburn Co-developed-by: Michael Reeves Signed-off-by: Michael Reeves --- arch/arm64/boot/dts/apple/t8122-j613.dts | 5 ++ arch/arm64/boot/dts/apple/t8122.dtsi | 70 ++++++++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8122-j613.dts b/arch/arm64/boot/dts/apple/t8122-j613.dts index 61ec12759c638b..7a346f3d9e5b5e 100644 --- a/arch/arm64/boot/dts/apple/t8122-j613.dts +++ b/arch/arm64/boot/dts/apple/t8122-j613.dts @@ -35,6 +35,11 @@ power-domains = <&ps_disp_cpu>, <&ps_dptx_ext_phy>; }; +&port00 { + bus-range = <1 1>; + pwren-gpios = <&smc_gpio 13 GPIO_ACTIVE_HIGH>; +}; + &fpwm1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8122.dtsi b/arch/arm64/boot/dts/apple/t8122.dtsi index 9e0761943660d5..49765a80b55988 100644 --- a/arch/arm64/boot/dts/apple/t8122.dtsi +++ b/arch/arm64/boot/dts/apple/t8122.dtsi @@ -559,6 +559,12 @@ ; }; + pcie_pins: pcie-pins { + // clkreq pins + pinmux = , + , + ; + }; }; pinctrl_nub: pinctrl@2e41f0000 { @@ -790,6 +796,70 @@ power-domain-names = "ans", "apcie_phy_sw"; resets = <&ps_ans>; }; + + pcie0_dart_0: iommu@594000000 { + compatible = "apple,t8122-dart", "apple,t8110-dart"; + reg = <0x5 0x94000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_st>; + }; + + pcie0: pcie@580000000 { + compatible = "apple,t8122-pcie", "apple,t6020-pcie"; + device_type = "pci"; + + reg = <0x5 0x80000000 0x0 0x1000000>, /* config */ + <0x5 0x91000000 0x0 0x4000>, /* rc */ + <0x5 0x94008000 0x0 0x4000>, /* port0 */ + <0x5 0x9e008000 0x0 0x4000>; /* phy0 */ + reg-names = "config", "rc", "port0", "phy0"; + + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 1075 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map = <0x100 &pcie0_dart_0 1 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 4>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>; + + power-domains = <&ps_apcie_gp>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + dma-coherent; + + port00: pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 187 GPIO_ACTIVE_LOW>; // perst + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port00 0 0 0 0>, + <0 0 0 2 &port00 0 0 0 1>, + <0 0 0 3 &port00 0 0 0 2>, + <0 0 0 4 &port00 0 0 0 3>; + }; + }; }; }; From 734b3de8d164cd992372b2b66b23795fecd8136a Mon Sep 17 00:00:00 2001 From: Michael Reeves Date: Sat, 31 Jan 2026 13:03:06 +1100 Subject: [PATCH 8/9] dt-bindings: iommu: apple: Add Apple M3 compatibles to DART and SART Apple Silicon Macs use two types of IOMMU, SART (for NVMe) and DART (for everything else). On M3 (t8122), the SART is compatible with the t6000 (M1 Pro/Max) one and the DART is compatible with the t8110 (A15) one. Thus, add a t8122 enum variant to the compatibles, but leave the base compatibles unchanged. Signed-off-by: Michael Reeves --- Documentation/devicetree/bindings/iommu/apple,dart.yaml | 4 +++- Documentation/devicetree/bindings/iommu/apple,sart.yaml | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/apple,dart.yaml b/Documentation/devicetree/bindings/iommu/apple,dart.yaml index 47ec7fa52c3ac6..e179199dbd3b54 100644 --- a/Documentation/devicetree/bindings/iommu/apple,dart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,dart.yaml @@ -29,7 +29,9 @@ properties: - apple,t8110-dart - apple,t6000-dart - items: - - const: apple,t6020-dart + - enum: + - apple,t6020-dart + - apple,t8122-dart - const: apple,t8110-dart reg: diff --git a/Documentation/devicetree/bindings/iommu/apple,sart.yaml b/Documentation/devicetree/bindings/iommu/apple,sart.yaml index 88e66d4b13c6bc..8fd7775704ab7d 100644 --- a/Documentation/devicetree/bindings/iommu/apple,sart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,sart.yaml @@ -33,6 +33,7 @@ properties: - enum: - apple,t6020-sart - apple,t8112-sart + - apple,t8122-sart - const: apple,t6000-sart - enum: - apple,t6000-sart From e320a6724150658e9cdf68933d0ac4b772ab3890 Mon Sep 17 00:00:00 2001 From: Michael Reeves Date: Sat, 31 Jan 2026 13:37:01 +1100 Subject: [PATCH 9/9] dt-bindings: mailbox: Add Apple M3 (t8122) compatible The mailbox on M3 (t8122) is compatible with asc-mailbox-v4, so add the t8122 compatible variant to enum section of the v4 mailbox section. Signed-off-by: Michael Reeves --- Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index 28985cc62c2539..a30d696dcfe42a 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -10,8 +10,7 @@ maintainers: - Hector Martin - Sven Peter -description: - The Apple mailbox consists of two FIFOs used to exchange 64+32 bit +description: The Apple mailbox consists of two FIFOs used to exchange 64+32 bit messages between the main CPU and a co-processor. Multiple instances of this mailbox can be found on Apple SoCs. One of the two FIFOs is used to send data to a co-processor while the other @@ -30,6 +29,7 @@ properties: - enum: - apple,t8103-asc-mailbox - apple,t8112-asc-mailbox + - apple,t8122-asc-mailbox - apple,t6000-asc-mailbox - apple,t6020-asc-mailbox - const: apple,asc-mailbox-v4